At the same time as performance and flexibility requirements of network interfaces are increasing, the expected levels of quality are also increasing, creating a need for more sophisticated and efficient test techniques to guarantee not only hardware functionality but design margin against the effects of aging, temperature variations, system noise and incoming signal degradation.
In contrast to rapidly changing system requirements to support multiple data rates and improved testability, the high-performance timing source technology used within these systems has failed to keep pace with the growing need for increased timing flexibility. Instead, timing subsystems remain tied to fixed frequency high-Q elements such as quartz crystals or surface acoustic wave (SAW) devices that meet the necessary performance requirements but lack the multi-frequency timing capability needed to support new services and test requirements. As a result, there is a growing need for new solutions to the problem of providing high-speed, low jitter clocks at the network interface.
Traditional multi-rate clock solutions System designers have been able to provide a limited degree of data rate flexibility while still employing existing clock source technology. These designs are typically faced with the challenge of multiplying a low frequency network synchronization clock up to multiple high-frequency reference clocks
Additionally, the timing subsystem must monitor the health of the network synchronization clocks while providing the capability to hitless switch between input references without causing phase transients on the transmit reference clock. To further complicate the timing subsystem design, sub picosecond (RMS) jitter clock requirements necessitate the use of jitter attenuating clock multiplier phase-locked loops (PLLs) of the type commonly constructed using discrete voltage-controlled SAW oscillators (VCSO) devices, phase detectors and loop filter elements. These PLL designs also need to support non-integer clock multiplication ratios needed for translation between base data rates and FEC line rates.
To support line cards with multiple data rates and FEC scaling ratios, designers rely on parallel instantiations of fixed multiplication ratio PLLs to produce the desired system clock rates. In these designs, the VCSO of each PLL is centered on the output clock frequency associated with each data rate and the RF multiplexer chooses only one of the PLL outputs at any given time. While this approach will support a small number of unique data rate choices, it does so at the cost of significant board area and component expense. Recently, some VCSO suppliers have introduced single packages that include two unique frequency VCSOs in order to reduce the board space penalty; however, this only provides incremental board space improvement and the solution still includes the cost of a separate resonator element for each unique output frequency/clock multiplication ratio combination. Alternatively, the system designer can specify a different bill of materials (BOM) for each data rate, creating a unique board type for each case. While this approach does not incur the board area penalty, as does the above parallel architecture, it does not allow for software provisioning of the service in the field and it increases the number of board types that must be kept in inventory. Also, neither approach provides any enhancement to the board test capability. System level timing architectures such as these have not changed much over time because of the lack of viable alternative technologies. The architectures have the appearance of being stopgap measures until more efficient solutions are found.
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